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1 ? fn6448.2 isl6313 two-phase buck pwm controller with integrated mosfet drivers for intel vr11 and amd applications the isl6313 two-phase pwm control ic provides a precision voltage regulation system for advanced microprocessors. the integration of power mosfet drivers into the controller ic marks a departure from the separate pwm controller and driver c onfiguration of previous multi-phase product families. by reducing the number of external parts, this integrati on is optimized for a cost and space saving power management solution. one outstanding feature of this controller ic is its multiprocessor compatibility, allowing it to work with both intel and amd microprocessors. included are programmable vid codes for intel vr11 as well as amd 5-bit and 6-bit dac tables. a circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. the output voltage can also be pos itively or negatively offset through the use of a single external resistor. the isl6313 also includes adv anced control loop features for optimal transient response to load apply and removal. one of these features is highly accurate, fully differential, continuous dcr current sensin g for load line programming and channel current balance. active pulse positioning (app) modulation and adaptive phas e alignment (apa) are two other unique features, allowing for quicker initial response to high di/dt load transients. with this quicker initial response to load transients, the number of output bulk capacitors can be reduced, helping to reduce cost. integrated into the isl6313 ar e user programmable current sense resistors, which require only a single external resistor to set their values. no external current sense resistors are required. another unique feat ure of the isl6313 is the addition of a dynamic vid compensation pin that allows optimizing compensation to be added for well controlled dynamic vid response. protection features of this c ontroller ic include a set of sophisticated overvoltage, un dervoltage, and overcurrent protection. furthermore, the isl6313 includes protection against an open circuit on the remote sensing inputs. combined, these features provid e advanced protection for the microprocessor and power system. features ? integrated multi-ph ase power conversion - 2-phase or 1-phase operation with internal drivers ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over-temperature - adjustable reference-voltage offset ? optimal transient response - active pulse positioning (app) modulation - adaptive phase alignment (apa) ? fully differential, continuous dcr current sensing - integrated programmable current sense resistors - accurate load line programming - precision channel current balancing ? variable gate drive bias: 5v to 12v ? multi-processor compatible - intel vr11 mode of operation - amd mode of operation ? microprocessor voltag e identification inputs - 8-bit dac - selectable between intel vr11, amd 5-bit, and amd 6-bit dac tables - dynamic vid technology ? dynamic vid compensation ? overcurrent protection ? multi-tiered overvoltage protection ? digital soft-start ? selectable operation frequency up to 1.5mhz per phase ? pb-free (rohs compliant) ordering information part number (note) part marking temp. (c) package (pb-free) pkg. dwg. # isl6313crz* isl6313 crz 0 to +70 36 ld 6x6 tqfn l36.6x6 isl6313irz* isl6313 irz -40 to +85 36 ld 6x6 tqfn l36.6x6 *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. september 2, 2008
2 fn6448.2 september 2, 2008 pinout isl6313 (36 ld tqfn) top view isl6313 integrated dr iver block diagram pgood ss fs isen1- isen2+ isen2- en isen1+ rset vcc vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 1 36 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 phase1 ugate1 boot1 lgate1 pvcc lgate2 boot2 ugate2 phase2 iout ref dvc apa comp fb ofs vsen rgnd 37 gnd through shoot- protection boot ugate phase lgate logic control gate pvcc 10k pwm soft-start and fault logic 20k isl6313 isl6313
3 fn6448.2 september 2, 2008 block diagram driver ss dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp rgnd vsen 1 n pwm1 boot1 ugate1 phase1 lgate1 pvcc boot2 ugate2 phase2 lgate2 soft-start and fault logic vcc reset power-on 0.85v en pgood gnd vid1 vid0 ch2 current sense channel current balance overvoltage detection logic undervoltage detection logic pwm2 mode / dac select i_avg mosfet driver mosfet adaptive phase allignment circuitry ocp i_trip i_avg ocp v ocp iout x1 apa isen2- isen2+ ch1 current sense isen1+ isen1- rset x2 dvc open sense line prevention clock and generator modulator waveform rgnd channel detect fs r isen2 r isen1 2k fs + - + - + + + + isl6313 isl6313
4 fn6448.2 september 2, 2008 typical application - isl6313 vid4 vid5 pgood vid3 vid2 vid1 vcc isl6313 vid0 fs ofs ref load en gnd vid6 vid7 ss +5v isen2- isen2+ isen1- isen1+ iout fb comp vsen rgnd dvc +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc rset apa +5v vcc isl6313 isl6313
5 fn6448.2 september 2, 2008 typical application - isl6313 with ntc thermal compensation load +5v +12v +12v ntc place in close proximity +5v vcc vid4 vid5 pgood vid3 vid2 vid1 vcc isl6313 vid0 fs ofs ref en gnd vid6 vid7 ss isen2- isen2+ isen1- isen1+ iout fb comp vsen rgnd dvc phase1 ugate1 boot1 lgate1 phase2 ugate2 boot2 lgate2 pvcc rset apa isl6313 isl6313
6 fn6448.2 september 2, 2008 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v boot voltage, v boot . . . . . . . . . . . . . . gnd - 0.3v to gnd + 36v boot to phase voltage, v boot-phase . . . . . . -0.3v to 15v (dc) -0.3v to 16v (<10ns, 10j) phase voltage, v phase . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot - phase = 12v) ugate voltage, v ugate . . . . . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate voltage, v lgate . . . . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc + 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v thermal information thermal resistance ja (c/w) jc (c/w) tqfn package (notes 1, 2) . . . . . . . . . 32 2.0 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature isl6313crz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c isl6313irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. limits established by characteri zation and are not production tested. electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter test conditions min typ max units bias supplies input bias supply current i vcc ; en = high 10 14 17 ma gate drive bias current - pvcc pin i pvcc ; en = high 2 4.2 6 ma vcc por (power-on reset) threshold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.87 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.75 3.87 4.00 v pwm modulator oscillator frequency accuracy, f sw (isl6313crz) r t = 100k (0.1%) 225 250 275 khz oscillator frequency accuracy, f sw (isl6313irz) r t = 100k (0.1%) 215 250 280 khz adjustment range of switching frequency (note 3) 0.08 - 1.0 mhz oscillator ramp amplitude, v p-p (note 3) - 1.50 - v control thresholds en rising threshold 0.84 0.85 0.88 v en hysteresis - 100 - mv reference and dac system accuracy (1.000v to 1.600v) -0.5 - 0.5 % system accuracy (0.600v to 1.000v) -1.0 - 1.0 % system accuracy (0.375v to 0.600v) -2.0 - 2.0 % dac input low voltage (intel) - - 0.4 v isl6313 isl6313
7 fn6448.2 september 2, 2008 dac input high voltage (intel) 0.8 - - v dac input low voltage (amd) - - 0.8 v dac input high voltage (amd) 1.4 - - v pin-adjustable offset ofs sink current accuracy (negative offset) r ofs = 32.4k from ofs to vcc 47.0 50.0 53.0 a ofs source current accuracy (positive offset) r ofs = 6.04k from ofs to gnd 47.0 50.0 53.0 a error amplifier dc gain r l = 10k to ground, (note 3) - 96 - db gain-bandwidth product c l = 100pf, r l = 10k to ground, (note 3) -40-mhz slew rate c l = 100pf, load = 400a, (note 3) - 20 - v/s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 1.30 1.52 v soft-start ramp soft-start ramp rate r s = 100k - 1.26 - mv/s adjustment range of soft-start ramp rate (note 3) 0.156 - 6.25 mv/s current sensing iout current sense offset r set = 40.2k , v isen1+ = v isen2+ = 0v -2.5 0 2.5 a iout current sense gain (isl6313crz) r set = 40.2k , v isen1 = v isen2 = 24mv768084a iout current sense gain (isl6313irz) r set = 40.2k , v isen1 = v isen2 = 24mv738084a overcurrent protection overcurrent trip level - average channel normal operation (isl6313crz) 88 100 112 a normal operation (isl6313irz) 82 100 118 a dynamic vid change 114 140 166 a overcurrent trip level - individual channel normal operation 114 140 166 a dynamic vid change 166 196 226 a iout pin overcurrent trip level 1.97 2.02 2.07 v protection undervoltage threshold vsen falling vdac - 325mv vdac - 350mv vdac - 375mv v undervoltage hysteresis vsen rising 85 100 125 mv overvoltage threshold during soft-start vr11 and amd 1.220 1.260 1.300 v overvoltage threshold vr11, vsen rising vdac + 150mv vdac + 175mv vdac + 200mv v amd, vsen rising vdac + 200mv vdac + 225mv vdac + 250mv v overvoltage hysteresis vsen falling - 100 - mv electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6313 isl6313
8 fn6448.2 september 2, 2008 timing diagram switching time (note 3) ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% -26-ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% -18-ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% -18-ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% -12-ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive -10-ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive -10-ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current 1.25 2.0 3.0 upper drive sink resistance v pvcc = 12v, 15ma sink current 0.9 1.65 3.0 lower drive source resistance v pvcc = 12v, 15ma source current 0.85 1.25 2.2 lower drive sink resistance v pvcc = 12v, 15ma sink current 0.60 0.80 1.35 over-temperature sh utdown (note 3) thermal shutdown setpoint - 160 - c thermal recovery setpoint - 100 - c electrical specifications recommended operating conditions, unless otherwise spec ified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate isl6313 isl6313
9 fn6448.2 september 2, 2008 functional pin description vcc vcc is the bias supply for the ics small-signal circuitry. connect this pin to a +5v supply and decouple using a quality 0.1f ceramic capacitor. pvcc this pin is the power supply pin for the channel mosfet drivers, and can be connected to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1.0f ceramic capacitor. gnd gnd is the bias and reference ground for the ic. en this pin is a threshold-sensitive (approximately 0.85v) enable input for the controller. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fs a resistor, r s , tied to this pin sets the channel switching frequency of the controller. refer to equation 47 for proper resistor calculation. the fs pin also controls whether the internal i avg current is connected to the fb pin or not. tying the r s resistor to ground connects the i avg current internally to the fb pin, allowing the converter to incorporate output voltage droop proportional to the output current. tying the r s resistor to vcc, disconnects the i avg current internally from the fb pin. vid0, vid1, vid2, vid3, vi d4, vid5, vid6, and vid7 these are the inputs for the inte rnal dac that provides the reference voltage for output regulation. these pins respond to ttl logic thresholds. these pins are internally pulled high, to approximately 1.2v, by 40a internal current sources for intel modes of operation, and pulled low by 20a internal current sources for amd modes of ope ration. the internal pull-up current decreases to 0 as the vid voltage approaches the internal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ic?s bias voltage (vcc). vsen this pin senses the microprocessor?s core voltage. connect this pin to the core voltage sense pin or point of the microprocessor. rgnd this pin senses the local ground voltage of the microprocessor and offsets the internal dac by this sensed voltage. connect this pin to the ground sense pin or point of the microprocessor. fb and comp these pins are the internal error amplifier inverting input and output respectively. the fb pin, comp pin, and the vsen pins are tied together thr ough external r-c networks to compensate the regulator. dvc a series resistor and capacitor can be connected from the dvc pin to the fb pin to compensate and smooth dynamic vid transitions. iout the iout pin is the average channel-current sense output. this pin is used as a load current indicator to monitor what the output load current is. this pin can also be used to set the overcurrent protection trip level if it desired that a lower level be used then the internal trip point. connecting this pin through a resistor to ground allows the controller to set the alternate overcurrent protection trip level. apa this is the adaptive phase alignment set pin. a 100a current flows into the apa pin and by tying a resistor from this pin to comp the trip level for the adaptive phase alignment circuitry can be set. ref the ref input pin is the positive input of the error amplifier. it is internally connected to the dac output through a 2k resistor. a capacitor is used between the ref pin and ground to smooth the voltage transition during soft-start and dynamic vid transitions. this pin can also be bypassed to rgnd if desired. rset connect this pin to vcc through a resistor to set the effective value of the internal r isen current sense resistors. it is recommended a 0.1f ceramic capacitor be placed in parallel with this resistor for noise immunization . ofs the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vsen. the offset current is generated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. isen1-, isen1+, i sen2-, and isen2+ these pins are used for differentially sensing the corresponding channel output currents. the sensed currents are used for channel balanc ing, protection, and load line regulation. connect isen1- and isen2- to the node between the rc sense elements surrounding the inductor of their respective isl6313 isl6313
10 fn6448.2 september 2, 2008 channel. tie the isen+ pins to the vcore side of their corresponding channel?s sense capacitor. tying isen2- to vcc programs the part for single phase operation. ugate1 and ugate2 connect these pins to the corresponding upper mosfet gates. these pins are used to control the upper mosfets and are monitored for shoot-through prevention purposes. boot1 and boot2 these pins provide the bias voltage for the corresponding upper mosfet drives. connect these pins to appropriately chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pin provides the necessary bootstrap charge. phase1 and phase2 connect these pins to the sources of the corresponding upper mosfets. these pins ar e the return path for the upper mosfet drives. lgate1 and lgate2 these pins are used to control the lower mosfets. connect these pins to the corresponding lower mosfets? gates. ss a resistor, r ss , placed from ss to ground or vcc, will set the soft-start ramp slope. refer to equations 20 and 21 for proper resistor calculation. the state of the ss pin also selects which of the available dac tables will be used to decode the vid inputs and puts the controller into the corresponding mode of operation. for intel vr11 mode of operation the r ss resistor should be tied to ground. amd compliance is selected if the r ss resistor is tied to vcc. pgood for intel mode of operation, pgood indicates whether vsen is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft -start. if vsen exceeds these limits, an overcurrent ev ent occurs, or if the part is disabled, pgood is pulled low. pgood is always low prio r to the end of soft-start. for amd modes of operation, pgood will always be high as long as vsen is within the specified undervoltage, overvoltage window and soft-s tart has ended. pgood only goes low if vsen is outside this window. operation multiphase power conversion microprocessor load current pr ofiles have changed to the point that using single-phase regu lators is no longer a viable solution. designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multi-phase converters can accomplish. the isl6313 controller helps simplify implementation by integrating vital functions and requiring minimal external components. the ?block diagram? on page 3 provides a top level view of multi-phase power conversion using the isl6313 controller. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the desig ner can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplic ative effect on output ripple frequency. the three channel currents (i l1 , i l2 , and i l3 ) combine to form the ac ripple current and the dc load current. the ripple component has 3x the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to-peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. figure 1. pwm and inductor-current waveforms for 3-phase converter 1 s/div pwm2, 5v/div pwm1, 5v/div i l2 , 7a/div i l1 , 7a/div i l1 + i l2 + i l3 , 7a/div i l3 , 7a/div pwm3, 5v/div (eq. 1) i pp v in v out ? () v out ? lf s v ? in ? --------------------------------------------------------- - = isl6313 isl6313
11 fn6448.2 september 2, 2008 the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms inpu t capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the si ngle-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. active pulse positioning (app) modulated pwm operation the isl6313 uses a proprietary active pulse positioning (app) modulation scheme to control the internal pwm signals that command each channel?s driver to turn their upper and lower mosfets on and off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is th e inverse of the switching frequency set by the resistor connected to the fs pin. the advantage of intersil?s proprietary active pulse positioning (app) modulator is that the pwm signal has the ability to turn on at any point during this pwm time interval, and turn off immediately after the pwm signal has transitioned high. this is important because it allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp minus the current correction signal relative to the proprie tary modulator ramp waveform as illustrated in figure 4. at the beginning of each pwm time interval, this modified v comp signal is compared to the internal modulator waveform. as long as the modified v comp voltage is lower then the modulator waveform voltage, the pwm signal is commanded low. the internal mosfet driver detects the low state of the pwm signal and turns off the upper mosfet and turns on the lower synchronous mosfet. when the modified v comp voltage crosses the modulator ramp, the pwm output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm signal will remain high until the modified v comp voltage crosses the modulator ramp again. when this occurs the pwm signal will transition low again. during each pwm time interval the pwm signal can only transition high once. once pwm transitions high it can not transition high again until the beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. adaptive phase alignment (apa) to further improve the transient response, the isl6313 also implements intersil?s proprietary adaptive phase alignment (apa) technique, which turns on all of the channels together at the same time during large current step transient events. (eq. 2) i cp-p () v in nv out ? ? () v out ? lf s v ? in ? ------------------------------------------------------------------- - = figure 2. channel input currents and input-capacitor rms current for 3-phase converter channel 1 input current channel 2 input current channel 3 input current input-capacitor current, 10a/div 1s/div figure 3. adaptive phase alignment detection external circuit isl6313 internal circuit comp v apa,trip error apa amplifier c apa r apa + - low filter - + apa pass 100a - + to apa circuitry isl6313 isl6313
12 fn6448.2 september 2, 2008 as figure 3 shows, the apa ci rcuitry works by monitoring the voltage on the apa pin and comparing it to a filtered copy of the voltage on the comp pin. the voltage on the apa pin is a copy of the comp pin volt age that has been negatively offset. if the apa pin exceeds the filtered comp pin voltage an apa event occurs and all of the channels are forced on. the apa trip level is the am ount of dc offset between the comp pin and the apa pin. this is the voltage excursion that the apa and comp pin must have during a transient event to activate the adaptive phase alignment circuitry. this apa trip level is set through a resistor, r apa , that connects from the apa pin to the comp pin. a 100a current flows across r apa into the apa pin to set the apa trip level as described in equation 3. an apa trip level of 500mv is recommended for most applications. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. number of ac tive channels the default number of active channels on the isl6313 is two for 2-phase operation. if single phase operation is desired the isen2- pin should be tied to the vcc pin. this will disable channel 2, so only channel 1 will fire. in single phase operation all of the channel 2 pins should be left unconnected including the phase2, lgate2, ugate2, boot2, and isen2+ pins. channel-current balance one important benefit of multi-phase operation is the thermal advantage gained by distributi ng the dissipated heat over multiple devices and greater area. by doing this the designer avoids the complexity of driving parallel mosfets and the expense of using expensive hea t sinks and exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry equal amounts of current at any load level. to achieve this, the currents through each channel must be sensed continuously every switching cycle. the sensed currents, i n , from each active channel are summed together and divided by the number of active channels. the resulting cycle average current, i avg , provides a measure of the total load-current demand on the c onverter during each switching cycle. channel-current balance is achieved by comparing the sensed current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patented current-balance method is illust rated in figure 4, with error correction for channel 1 repres ented. in the fi gure, the cycle average current, i avg , is compared with the channel 1 sensed current, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. continuous current sensing in order to realize proper cu rrent-balance, the currents in each channel are sensed continuously every switching cycle. during this time the cu rrent-sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the isl6313 supports inductor dcr current sensing to continuously sense each channel?s current for channel-current balance. the internal circuitry, shown in figure 6 represents channel n of an n-channel converter. this circuitry is repeated for ea ch channel in the converter, but may not be active depending on how many channels are operating. v apa trip () r apa 100 10 6 ? ? = (eq. 3) figure 4. channel-1 pwm function and current-balance adjustment 2 i avg i 2 - + + - + - f(s) pwm1 i 1 v comp i er filter to gate control logic modulator ramp waveform + + figure 5. continuous current sampling time pwm i l i sen switching period isl6313 isl6313
13 fn6448.2 september 2, 2008 inductor windings have a characteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 6. the channel current i l , flowing through the inductor, passes through the dcr. equation 4 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor (r 1 and c) extracts the dcr voltage, as shown in figure 6. the voltage across the sense capacitor, v c , can be shown to be proportional to the channel current i l , shown in equation 5. if the r 1 -c 1 network components are selected such that their time constant matches the inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr. the capacitor voltage v c , is then replicated across the effective internal sense resistance r isen . this develops a current through r isen which is proportional to the inductor current. this current, i sen , is continuously sensed and is then used by the controller for load-line regulation, channel-current balancing, and overcurrent detection and limiting. equation 6 shows that the proportion between the channel-current, i l , and the sensed current, i sen , is driven by the value of the effective sense resistance, r isen , and the dcr of the inductor. the effective internal r isen resistance is important to the current sensing process because it sets the gain of the load line regulation loop as well as the gain of the channel-current balance loop and the overcurrent trip level. the effective internal r isen resistance is user programmable and is set through use of the rset pin. placing a single resistor, r set , from the rset pin to the vcc pin programs the effective internal r isen resistance according to equation 7. it is important to note that the r set resistance value must be between 20k and 80k for equation 7 to be valid. output voltage setting the isl6313 uses a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the vid pins. the dac decodes the logic signals into one of the discrete voltages shown in tabl es 2, 3 or 4. in the intel vr11 mode of operation, each vid pin is pulled up to an internal 1.2v voltage by a weak current source (40a), which decreases to 0a as the voltage at the vid pin varies from 0 to the internal 1.2v pull-up voltage. in amd modes of operation the vid pins are pulled low by a week 20a current source. external pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5v. . the isl6313 accommodates th ree different dac ranges: intel vr11, amd k8/k9 5-bit, and amd 6-bit. the state of the ss and vid7 pins decide which dac version is active. refer to table 1 for a description of how to select the desired dac version. figure 6. inductor dcr current sensing configuration i n - + isen- sense isl6313 internal v in ugate r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen v c (s) + - isen+ lgate mosfet driver rset r set vcc circuit v l s () i l sl dcr + ? () ? = (eq. 4) v c s () sl ? dcr ------------- 1 + ?? ?? sr 1 c 1 ?? 1 + () ----------------------------------------- dcr i l ? ? = (eq. 5) table 1. isl6313 dac select table dac version ss pin vid7 pin intel vr11 r ss resistor tied to gnd - amd 5-bit r ss resistor tied to vcc high amd 6-bit r ss resistor tied to vcc low table 2. vr11 voltage identification codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 00000000off 00000001off 000000101.6 0000 000000111.5 9375 i sen i l dcr r isen ----------------- - ? = (eq. 6) r isen 3 400 --------- - r set ? = (eq. 7) *note: r set must be between 20k and 80k isl6313
14 fn6448.2 september 2, 2008 000001001. 58750 000001011. 58125 000001101. 57500 000001111. 56875 000010001. 56250 000010011. 55625 000010101. 55000 000010111. 54375 000011001. 53750 000011011. 53125 000011101. 52500 000011111. 51875 000100001. 51250 000100011. 50625 000100101. 50000 000100111. 49375 000101001. 48750 000101011. 48125 000101101. 47500 000101111. 46875 000110001. 46250 000110011. 45625 000110101. 45000 000110111. 44375 000111001. 43750 000111011. 43125 000111101. 42500 000111111. 41875 001000001. 41250 001000011. 40625 001000101. 40000 001000111. 39375 001001001. 38750 001001011. 38125 001001101. 37500 001001111. 36875 001010001. 36250 001010011. 35625 001010101. 35000 001010111. 34375 table 2. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 001011001. 33750 001011011. 33125 001011101. 32500 001011111. 31875 001100001. 31250 001100011. 30625 001100101. 30000 001100111. 29375 001101001. 28750 001101011. 28125 001101101. 27500 001101111. 26875 001110001. 26250 001110011. 25625 001110101. 25000 001110111. 24375 001111001. 23750 001111011. 23125 001111101. 22500 001111111. 21875 010000001. 21250 010000011. 20625 010000101. 20000 010000111. 19375 010001001. 18750 010001011. 18125 010001101. 17500 010001111. 16875 010010001. 16250 010010011. 15625 010010101. 15000 010010111. 14375 010011001. 13750 010011011. 13125 010011101. 12500 010011111. 11875 010100001. 11250 010100011. 10625 010100101. 10000 010100111. 09375 table 2. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6313
15 fn6448.2 september 2, 2008 010101001.08750 010101011.08125 010101101.07500 010101111.06875 010110001.06250 010110011.05625 010110101.05000 010110111.04375 010111001.03750 010111011.03125 010111101.02500 010111111.01875 011000001.01250 011000011.00625 011000101.00000 011000110.99375 011001000.98750 011001010.98125 011001100.97500 011001110.96875 011010000.96250 011010010.95625 011010100.95000 011010110.94375 011011000.93750 011011010.93125 011011100.92500 011011110.91875 011100000.91250 011100010.90625 011100100.90000 011100110.89375 011101000.88750 011101010.88125 011101100.87500 011101110.86875 011110000.86250 011110010.85625 011110100.85000 011110110.84375 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 011111000.8 3750 011111010.8 3125 011111100.8 2500 011111110.8 1875 100000000.8 1250 100000010.8 0625 100000100.8 0000 100000110.7 9375 100001000.7 8750 100001010.7 8125 100001100.7 7500 100001110.7 6875 100010000.7 6250 100010010.7 5625 100010100.7 5000 100010110.7 4375 100011000.7 3750 100011010.7 3125 100011100.7 2500 100011110.7 1875 100100000.7 1250 100100010.7 0625 100100100.7 0000 100100110.6 9375 100101000.6 8750 100101010.6 8125 100101100.6 7500 100101110.6 6875 100110000.6 6250 100110010.6 5625 100110100.6 5000 100110110.6 4375 100111000.6 3750 100111010.6 3125 100111100.6 2500 100111110.6 1875 101000000.6 1250 101000010.6 0625 101000100.6 0000 101000110.5 9375 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6313
16 fn6448.2 september 2, 2008 101001000.58750 101001010.58125 101001100.57500 101001110.56875 101010000.56250 101010010.55625 101010100.55000 101010110.54375 101011000.53750 101011010.53125 101011100.52500 101011110.51875 101100000.51250 101100010.50625 101100100.50000 11111110off 11111111off table 3. amd 5-bit voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111100.800 111010.825 111000.850 110110.875 110100.900 110010.925 110000.950 101110.975 101101.000 101011.025 101001.050 100111.075 100101.100 100011.125 100001.150 011111.175 011101.200 011011.225 011001.250 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 010111.275 010101.300 010011.325 010001.350 001111.375 001101.400 001011.425 001001.450 000111.475 000101.500 000011.525 000001.550 table 4. amd 6-bit voltage identification codes vid5 vid4 vid3 vid2 vid1 vid0 vdac 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 000010 1.5000 000011 1.4750 000100 1.4500 000101 1.4250 000110 1.4000 000111 1.3750 001000 1.3500 001001 1.3250 001010 1.3000 001011 1.2750 001100 1.2500 001101 1.2250 001110 1.2000 001111 1.1750 010000 1.1500 010001 1.1250 010010 1.1000 010011 1.0750 010100 1.0500 010101 1.0250 010110 1.0000 010111 0.9750 011000 0.9500 011001 0.9250 table 3. amd 5-bit voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vdac isl6313
17 fn6448.2 september 2, 2008 voltage regulation the integrating compensation network shown in figure 7 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl6313 to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is used by the modulator to generate the pwm signals. the pwm signals control the timing of the internal mosfet drivers and regulate the converter output so that the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 8. the internal and external circuitry that controls voltage regulation is illustrated in figure 7. the isl6313 incorporates differential remote-sense amplification in the feedback path. the differential sensing removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. load-line (droop) regulation some microprocessor manufacturers require a precisely-controlled output resi stance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. 011010 0.9000 011011 0.8750 011100 0.8500 011101 0.8250 011110 0.8000 011111 0.7750 100000 0.7625 100001 0.7500 100010 0.7375 100011 0.7250 100100 0.7125 100101 0.7000 100110 0.6875 100111 0.6750 101000 0.6625 101001 0.6500 101010 0.6375 101011 0.6250 101100 0.6125 101101 0.6000 101110 0.5875 101111 0.5750 110000 0.5625 110001 0.5500 110010 0.5375 110011 0.5250 110100 0.5125 110101 0.5000 110110 0.4875 110111 0.4750 111000 0.4625 111001 0.4500 111010 0.4375 111011 0.4250 111100 0.4125 111101 0.4000 111110 0.3875 111111 0.3750 table 4. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac v out v ref v ofs ? v droop ? = (eq. 8) vid ref figure 7. output voltage and load-line regulation with offset adjustment i avg external circuit isl6313 internal circuit comp r c r fb fb vsen - + (v droop + v ofs ) error v out v comp c c c ref - + 2k amplifier i ofs dac rgnd - + + + isl6313
18 fn6448.2 september 2, 2008 in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper s pecification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well cont rolled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 7, a current proportional to the average current of all active channels, i avg , flows from fb through a load-line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droo p with a steady-state value defined as equation 9: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a func tion of load current is derived by combining equations 6, 8, and 9. in equation 10, v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the internal sense resistor connected to the isen+ pin, r fb is the feedback resistor, n is the active channel number, and dcr is the inductor dcr value. therefore the equivalent loadl ine impedance, i.e. droop impedance, is equal to: output-voltage offset programming the isl6313 allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin, providing a negative offset. if r ofs is connected to ground, the voltage across it is regulated to 0.3v, and i ofs flows into the fb pin and out of the ofs pin, providing a positive offset. the offset current flowing through the resistor between vsen and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 8 and 9. once the desired output offset voltage has been determined, use equations 12 and 13 to set r ofs : for negative offset (connect r ofs to vcc): for positive offset (connect r ofs to gnd): (eq. 9) v droop i avg r fb ? = (eq. 10) v out v ref v ofs ? i out n ------------- dcr r isen ----------------- - r fb ?? ?? ?? ?? ? = r ll r fb n ------------ dcr r isen ----------------- - ? = (eq. 11) (eq. 12) r ofs 1.6 r fb ? v offset -------------------------- = (eq. 13) r ofs 0.3 r fb ? v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.3v 1.6v gnd r ofs r fb vsen isl6313 figure 8. positive offset output voltage programming vref v ofs + - i ofs e/a fb ofs vcc gnd + - + - 0.3v 1.6v vcc r ofs r fb vsen isl6313 figure 9. negative offset output voltage programming vref v ofs + - i ofs isl6313
19 fn6448.2 september 2, 2008 dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the isl6313 to do this by making changes to the vid inputs. the isl6313 is required to monitor the dac inputs and respond to on-the-fly vid changes in a co ntrolled manner, supervising a safe output voltage transition without discontinuity or disruption. the dac mode the isl6313 is operating in, determines how the controller responds to a dynamic vid change. intel dynamic vid transitions when in intel vr11 mode the isl6313 checks the vid inputs on the positive edge of an internal 5.5mhz clock. if a new code is established and it remains stable for 3 consecutive readings (0.36s to 0.54s), the isl6313 recognizes the new code and changes the internal da c reference directly to the new level. the intel processor controls the vid transitions and is responsible for incrementing or decrementing one vid step at a time. in vr11 mode, the isl6313 will immediately change the internal dac reference to the new requested value as soon as the request is validat ed, which means the fastest recommended rate at which a bit change can occur is once every 1s. if the vid code is changed by more then one step at a time, the dac will try to track it at a 5.5mhz step rate. this will likely cause an over current or overvoltage fault. amd dynamic vid transitions when running in amd 5-bit or 6-bit modes of operation, the isl6313 responds differently to a dynamic vid change then when in intel vr11 mode. in the amd modes the isl6313 still checks the vid inputs on the positive edge of an internal 5.5mhz clock. in these modes the vid code can be changed by more than a 1-bit step at a time. if a new code is established and it remains stable for 3 consecutive readings (0.36s to 0.54s), the isl6313 recognizes the change and begins slewing the dac in 6.25mv steps at a stepping frequency of 345khz until the vid and dac are equal. thus, the total time required for a vid change, t dvid , is dependent only on the size of the vid change ( v vid ). the time required for a isl6313-based converter in amd 5-bit dac configuration to make a 1.1v to 1.5v reference voltage change is about 186s, as calculated using equation 14. vid ?off? dac codes both the intel vr11 and the amd 5-bit vid tables include ?off? dac codes, which indicate to the controller to disable all regulation. recognition of these codes is slightly different in that they must be stable for 4 cons ecutive readings of a 5.5mhz clock (0.54s to 0.72s) to be recognized. once an ?off? code is recognized the isl6313 latches off, and must be reset by dropping the en pin. compensating dynamic vid transitions during a vid transition, the resulting change in voltage on the fb pin and the comp pin causes an ac current to flow through the error amplifier compensation components from the fb to the comp pin. this current then flows through the feedback resistor, r fb , and can cause the output voltage to overshoot or undershoot at the end of the vid transition. in order to ensure the smooth trans ition of the output voltage during a vid change, a vid-on-the-fly compensation network is required. this netw ork is composed of a resistor and capacitor in series, r dvc and c dvc , between the dvc and the fb pin. this vid-on-the-fly compen sation network works by sourcing ac current into the fb node to offset the effects of the ac current flowing from t he fb to the comp pin during a vid transition. to create th is compensation current the isl6313 sets the voltage on the dvc pin to be 2x the voltage on the ref pin. since the error amplifier forces the voltage on the fb pin and the ref pin to be equal, the resulting voltage across the series rc between dvc and fb is equal to the ref pin voltage. the rc compensation components, r dvc and c dvc , can then be selected to create the desired amount of compensation current. the amount of compensation current required is dependant on the modulator gain of t he system, k1, and the error amplifier r-c components, r c and c c , that are in series between the fb and comp pins. use equations 15, 16, and 17 to calculate the rc component values, r dvc and c dvc , for the vid-on-the-fly compensation network. for these equations: v in is the input voltage for the power train; v p-p is the oscillator ramp amplitude (1.5v); and r c and c c are the error amplifier r-c components between the fb and comp pins. (eq. 14) t dvid 1 345 10 3 ------------------------- - v vid 0.00625 --------------------- ?? ?? ? = figure 10. dynamic vid compensation network isl6313 internal circuit error ref amplifier c dvc r dvc - + x2 c c r c c ref dvc fb comp r fb vsen i dvc i c i dvc = i c v dac + r gnd k1 v in v p-p ------------ = (eq. 15) a k1 k1 1 ? ---------------- - = r dvc ar c = (eq. 16) c dvc c c a ------- - = (eq. 17) isl6313
20 fn6448.2 september 2, 2008 advanced adaptive zero shoot-through deadtime control (patent pending) the integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lowe r mosfet, the phase voltage is monitored until it reaches a -0.3v/+0.8v (forward/reverse inductor current). at this time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage preventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. when lgate first begins to transition low, this quick transition can disturb the phase node and cause a false trip, so there is 20ns of blanking time once lgate falls until phase is monitored. once the phase is high , the advanced adaptive shoot-through circuitry mo nitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase fall s to less than +0.8v, the lgate is released to turn-on. internal bootstrap device all three integrated drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins comple tes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 4v and its capacitance value can be chosen from equation 18: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. gate drive voltage versatility the isl6313 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. initialization prior to initialization, proper conditions must exist on the en, vcc, pvcc and the vid pins. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of oper ation, the controller asserts pgood. enable and disable while in shutdown mode, the lgate and ugate signals are held low to assure the mosfets remain off. the following input conditions must be met (for both intel and amd modes of operation) before the isl6313 is released 50nc 20nc figure 11. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 18) figure 12. power sequencing using threshold-sensitive enable (en) function external circuit isl6313 internal circuit - + 0.85v en +12v por circuit 10.7k 1.40k enable comparator soft-start and fault logic vcc pvcc isl6313
21 fn6448.2 september 2, 2008 from shutdown mode to begin the soft-start startup sequence: 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6313 is guaranteed. hyst eresis between the rising and falling thresholds assure that once enabled, the isl6313 will not inadvertently turn off unless the bias voltage drops substantia lly (see ?electrical specifications? on page 6). 2. the voltage on en must be above 0.85v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6313 in shutdown until the voltage at en rises above 0.85v. the enable comparator has 110mv of hysteresis to prevent bounce. 3. the driver bias voltage applied at the pvcc pin must reach the internal power-on reset (por) rising threshold. hysteresis between the rising and falling thresholds assure that once enabled, the isl6313 will not inadvertently turn off unless the pvcc bias voltage drops substantially (see ?electrica l specifications? on page 6). for intel vr11 and amd 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence. if running in amd 5-bit mode of operation there is one more condition that must be met: 4. the vid code must not be 11111 in amd 5-bit mode. this code signals the controller th at no load is present. the controller will not allow soft-start to begin if this vid code is present on the vid pins. once all of these conditions ar e met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level. intel soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. the soft-start seque nce for the intel modes of operation is slightly different then the amd soft-start sequence. for the intel vr11 mode of operation, the soft-start sequence if composed of four periods, as shown in figure 13. once the isl6313 is released from shutdown and soft-start begins (as described in ?enable and disable? on page 20), the controller will have a fixed delay period td1 of typically 1.10ms. after this delay period, the vr will begin first soft-start ramp until the output voltage reaches 1.1v vboot voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed delay period t d3 , of typically 93s. at the end of t d3 period, isl6313 will read the vid signals. it is recommended that the vid codes be set no later then 50s into period t d3 . if the vid code is valid, isl6313 will initiate the second soft-start ramp until the output voltage reaches the vid voltage plus/minus any offset or droop voltage. the soft-start time is the sum of the 4 periods as shown in equation 19. during t d2 and t d4 , isl6313 digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of t he soft-start oscillator which is defined by the resistor r ss on the ss pin. the second soft-start ramp time t d2 and t d4 can be calculated based on equations 20 and 21: for example, when vid is set to 1.5v and the r ss is set at 100k , the first soft-start ramp time t d2 will be 880s and the second soft-start ramp time t d4 will be 320s. after the dac voltage reaches the final vid setting, pgood will be set to high with the fixed delay t d5 . the typical value for t d5 is 93s. amd soft-start for the amd 5-bit and 6-bit modes of operation, the soft-start sequence is composed of two periods, as shown in figure 14. at the beginning of soft-start, the vid code is immediately obtained from the vid pins, followed by a fixed delay period t da of typically 1.10ms. after this delay period the isl6313 will begin ramping the output voltage to the desired dac level at a fixed ra te of 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor r ss on the ss pin. the amount of time required to ramp the output t ss t d1 t d2 t d3 t d4 +++ = (eq. 19) figure 13. soft-start waveforms v out , 500mv/div en 500s/div t d1 t d3 t d4 t d5 pgood t d2 (eq. 20) t d2 1.1 r ? ss 810 3 ? s () ?? = (eq. 21) t d4 v vid 1.1 ? r ss 810 3 ? s () ??? = isl6313
22 fn6448.2 september 2, 2008 voltage to the final dac voltage is referred to as t db , and can be calculated as shown in equation 22: at the end of soft-start, pgood will immediately go high if the vsen voltage is within the undervoltage and overvoltage limits. pre-biased soft-start the isl6313 also has the ability to start up into a pre-charged output, without causing any unnec essary disturbance. the fb pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin po tential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the dac setting. should the output be pre-charged to a level exceeding the dac setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the dac-set level. fault monitoring and protection the isl6313 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. the schematic in figure 16 outlines the interaction between the fault monitors and the power good signal. power good signal the power good pin (pgood) is an open-drain logic output that signals whether or not the isl6313 is regulating the output voltage within the proper levels, and whether any fault conditions exist. this pin should be tied through a resistor to a voltage source that?s equal to or less then vcc. for intel mode of operation, pgood indicates whether vsen is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft-start. pgood transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when t he controller is disabled by a reset from en, por, or one of the no-cpu vid codes. in the event of an overvoltage or overcurrent condition, or a no-cpu vid code, the controller latches off and pgood will not return high until en is toggled and a successful soft-start is (eq. 22) tdb v vid r ? ss 810 3 ? s () ?? = figure 14. soft-start waveforms v out , 500mv/div en 500s/div t da t db pgood figure 15. soft-start waveforms for isl6313-based multi-phase converter en (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level figure 16. power good and protection circuitry - + vdac + rgnd - + ovp uv pgood soft-start, fault and control logic 1.260v isl6313 internal circuitry vsen +175mv +225mv ss - + v ocp ocp - + ocl i 1 repeat for each channel 140a iout - + 100a i avg ocp or -350mv vdac + rgnd isl6313
23 fn6448.2 september 2, 2008 completed. in the case of an undervoltage event, pgood will return high when the output voltage rises above the undervoltage hysteresis level. pgood is always low prior to the end of soft-start. for amd modes of operation, pgood will always be high as long as vsen is within the specified undervoltage, overvoltage window and soft-s tart has ended. pgood only goes low if vsen is outside this window. even if the controller is shut down the pg ood signal will still stay high until vsen falls below th e undervoltage threshold. overvoltage protection the isl6313 constantly monito rs the difference between the v sen and r gnd voltages to detect if an overvoltage event occurs. during soft-start, while the dac is ramping up, the overvoltage trip level is the hig her of a fixed voltage 1.260v or dac + 175mv for intel modes of operation and dac + 225mv for amd modes of operation. upon successful soft-start, the overvoltage trip level is on ly dac + 175mv or dac + 225mv depending on whether the controller is running in intel or amd mode. when the output voltage rises above the ovp trip level actions are taken by the isl631 3 to protect the microprocessor load. at the inception of an overvoltage event, l gate1 and l gate2 are commanded high and the pgood signal is driven low. this turns on the all of the lower mosfets and pulls the output voltage below a level that might cause damage to the load. the l gate outputs remain high until v sen falls 100mv below the ovp threshold that tripped the overvoltage protection circuitry. the isl6313 will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends the isl6313 latches off, and must be reset by toggling en, or through por, before a soft -start can be reinitiated. there is an ovp condition that ex ists that will not latch off the isl6313. during a soft-start sequence, if the v sen voltage is above the ovp threshold an overvoltage event will occur, but will be released once v sen falls 100mv below the ovp threshold. if v sen then rises above the ovp trip threshold a second time, the isl6313 will be latched off and cannot be restarted until the controller is reset. pre-por overvoltage protection prior to p vcc and vcc exceeding their por levels, the isl6313 is designed to protect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvoltage event ceases or the input power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. in the event that during normal operation the p vcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events. undervoltage detection the undervoltage threshold is set at dac - 350mv of the vid code. when the output voltage (v sen - r gnd ) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. pgood will return high if the output voltage rises above dac - 250mv. open sense line prevention in the case that either of the remote sense lines, vsen or gnd, become open, the isl6313 is designed to prevent the controller from regulating. this is accomplished by means of a small 5a pull-up current on vsen, and a pull-down current on rgnd. if the sense lines are opened at any time, the voltage difference between v sen and r gnd will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controller stops regulating. the isl6313 will be latched off and cannot be restarted until the controller is reset. overcurrent protection the isl6313 takes advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. two different methods of detecting overcurrent events are availa ble on the isl6313. the first method continually compares the average sense current with a constant 100a ocp reference current as shown in figure 16. once the average sense current exceeds the ocp reference current, a comparator triggers the converter to begin overcurrent protection procedures. for this first method the overcurrent trip threshold is dictated by the dcr of the inductors, the number of active channels, and the rset pin resistor, r set . to calculate the overcurrent trip level, i ocp , using this method use equation 23, where n is the num ber of active channels, dcr is the individual inductor?s dcr, and r set is the rset pin resistor value. during vid-on-the-fly transitions the overcurrent trip level for this method is boosted to prevent false overcurrent trip events that can occur. starting from the beginning of a dynamic vid transition, the over current trip level is boosted to 140a. the ocp level will stay at this boosted level until 50s after the end of the dynam ic vid transition, at which point it will return to the typical 100a trip level. the second method for detecting overcurrent events continuously compares the vo ltage on the iout pin, v iout , to the overcurrent protection voltage, v ocp , as shown in figure 16. the average channel sense current flows out the iout pin and through r iout , creating the iout pin voltage which is proportional to the output current. when the iout i ocp 100 10 6 ? r set n3 ?? ?? dcr 400 ? --------------------------------------------------------------- = (eq. 23) isl6313
24 fn6448.2 september 2, 2008 pin voltage exceeds the v ocp voltage of 2.0v, the overcurrent protection circuitry activates. since the iout pin voltage is proportional to the output current, the overcurrent trip level, i ocp , can be set by selecting the proper value for r iout , as shown in equation 24. once the output current exceeds the overcurrent trip level, v iout will exceed v ocp and a comparator will trigger the converter to begin overcurr ent protection procedures. at the beginning of an overcurrent shutdown, the controller turns off both upper and lower mosfets and lowers pgood. the controller will then immediately attempt to soft- start. if the overcurrent fault re mains, the trip-retry cycles will continue until either the controller is disabled or the fault is cleared. if five overcurrent events occur without successfully completing soft-start, the controller will latch off after the fifth try and must be reset by toggling en before a soft-start can be reinitiated. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. individual channel overcurrent limiting the isl6313 has the ability to limit the current in each individual channel without shutting down the entire regulator. this is accomplished by cont inuously comparing the sensed currents of each channel with a constant 140a ocl reference current as shown in figure 17. if a channel?s individual sensed current exceeds this ocl limit, the ugate signal of that channel is immediately forced low, and the lgate signal is forced high. this turns off the upper mosfet(s), turns on the lowe r mosfet(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. that channel?s ugate signal will not be able to return high until the sensed channel current falls back below the 140a reference. during vid-on-the-fly transitions the ocl trip level is boosted to prevent false overcu rrent limiting events that can occur. starting from the beginning of a dynamic vid transition, the overcurrent trip level is boosted to 196a. the ocl level will stay at this boosted level until 50s after the end of the dynamic vid transition, at which point it will return to the typical 140a trip level. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include sc hematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole co mponents are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical soluti ons are those in which each phase handles between 25a and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but thes e designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 25, i m is the maximum continuous output current, i p-p is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the i ocp 6r set n ?? dcr r iout 400 ?? -------------------------------------------------- - = (eq. 24) 0a 0v output current, 50a/div figure 17. overcurrent behavior in hiccup mode output voltage, 500mv/div (eq. 25) p low 1 () r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lp-p () 2 1d ? () ? 12 --------------------------------------- - + ? = isl6313
25 fn6448.2 september 2, 2008 lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mo sfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low(1) and p low(2) . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 27, the required time for this commutation is t 1 and the approximated associated power loss is p up(1). . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 28, the approximate power loss is p up(2). . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up(3) . finally, the resistive part of the upper mosfet is given in equation 30 as p up(4). . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 27, 28, 29 and 30. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipa ted in the integrated drivers located in the controller. sinc e there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of +125c. the maximum allowable ic power dissipation for the 6x6 qfn pa ckage is approximately 3.5w at room temperature. see ?layout considerations? on page 31 for thermal transfer improvement suggestions. when designing the isl6313 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets a nd the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 31 and 32, respectively. in equations 31 and 32, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. (eq. 26) p low 2 () v don () f s i m n ------ i p-p 2 ----------- + ?? ?? ?? t d1 ? i m n ------ i p-p 2 ----------- ? ?? ?? ?? ?? t d2 ? + ?? = (eq. 27) p up 1 () v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? p up 2 () v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? (eq. 28) p up 3 () v in q rr f s ?? = (eq. 29) p up 4 () r ds on () d i m n ----- - ?? ?? ?? 2 i p-p 2 12 ---------- + ?? (eq. 30) p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 31) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 32) isl6313
26 fn6448.2 september 2, 2008 the total gate drive power loss es are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the pow er dissipated in the upper drive path resistance, p dr_up , the lower drive path resistance, p dr_up , and in the boot strap diode, p boot . the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 18 and 19 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as equation 33: inductor dcr current sensing component selection the isl6313 senses each individual channel?s inductor current by detecting the volt age across the output inductor dcr of that channel (as described in the ?continuous current sensing? on page 12). as fi gure 20 illustrates, an r-c network is required to accura tely sense the inductor dcr voltage and convert this information into a current, which is proportional to the total output current. the time constant of this r-c network must match the time constant of the inductor l/dcr. follow the steps below to choose the component values for this rc network. 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, and the value for c 1 chosen in step 1 into equation 34, to calculate the value for r 1 . once the r-c network components have been chosen, the effective internal r isen resistance must then be set. the r isen resistance sets the gain of the load line regulation loop as well as the gain of t he channel-current balance loop and the overcurrent trip level. the effective internal r isen resistance is set through a single resistor on the rset pin, r set . use equation 35 to calculate the value of r set . in this equation, dcr is the dcr of the output inductor at room temperature, i ocp is the desired overcurrent trip level, and n is the number of phases. it is recommended that the figure 18. typical upper-gate drive turn-on path figure 19. typical lower-gate drive turn-on path q 1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q 2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 33) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = r 1 l dcr c 1 ? ------------------------- = (eq. 34) figure 20. dcr sensing configuration i n - + isen- sense isl6313 internal v in ugate r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen v c (s) + - isen+ lgate mosfet driver rset r set vcc circuit isl6313
27 fn6448.2 september 2, 2008 desired overcurrent trip level, i ocp , be chosen so that it?s 30% larger then the maximum load current expected. due to errors in the inductance or dcr it may be necessary to adjust the value of r 1 to match the time constants correctly. the effects of time co nstant mismatch can be seen in the form of droop overs hoot or undershoot during the initial load transient spike, as shown in figure 21. follow the steps below to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). fo r example, with l = 1h and dcr = 1m , set the oscilloscope to 500s/div. 2. record v1 and v2 as shown in figure 21. 3. select new values, r 1(new) , for the time constant resistor based on the original value, r 1(old) , using equation 36. 4. replace r 1 with the new value and check to see that the error is corrected. repeat the procedure if necessary. loadline regulation resistor if loadline regulation is desired, the resistor on the fs pin, r t , should be connected to ground in order for the internal average sense current to fl ow out across the loadline regulation resistor, labeled r fb in figure 7. this resistor?s value sets the desired loadline required for the application. the desired loadline, r ll , can be calculated by equation 37 where v droop is the desired droop voltage at the full load current i fl. . based on the desired loadline, the loadline regulation resistor, r fb , can be calculated from equation 38. in equation 38, r ll is the loadline resistance; n is the number of active channels; dcr is the dcr of the individual output inductors; and r set is the rset pin resistor. if no loadline regulation is required, the resistor on the fs pin, r t , should be connected to the vcc pin. to choose the value for r fb in this situation, please refer to ?compensation without load-line regulation? on page 28. iout pin resistor a copy of the average sense cu rrent flows out of the iout pin, and a resistor, r iout , placed from this pin to ground can be used to set the overcurrent protection trip level. based on the desired overcurrent trip threshold, i ocp , the iout pin resistor, r iout , can be calculated from equation 39. apa pin component selection a 100a current flows into the apa pin and across r apa to set the apa trip level. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. use equation 40 to set r apa to get the desired apa trip level. an apa trip level of 500mv is recommended for most applications. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation as described in load-line regulation, there are two distinct methods for achieving these goals. compensation with load-line regulation the load-line regulated converter behaves in a similar manner to a peak current m ode controller because the two poles at the output filt er l-c resonant frequency split with the introduction of current informat ion into the control loop. the final location of th ese poles is determ ined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . r set dcr 100 10 6 ? ---------------------------- i ocp n ------------- - 400 3 --------- - ?? = (eq. 35) *note: r set must be between 20k and 80k r 1new () r 1old () v 1 v 2 ---------- ? = (eq. 36) figure 21. time constant mismatch behavior v 1 v out i tran v 2 i r ll v droop i fl ------------------------ - = (eq. 37) r fb r ll nr set ?? dcr --------------------------------------- 3 400 --------- - ? = (eq. 38) *note: r fb must be not exceed 4.0k (eq. 39) r iout r set n ? dcr i ocp ? -------------------------------- 6 400 --------- - ? = r apa v apa trip () 100 10 6 ? -------------------------------- - 500mv 100 10 6 ? ---------------------------- - 5k === (eq. 40) isl6313
28 fn6448.2 september 2, 2008 since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equatio n becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. tr eating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth fo r the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. in equation 41, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in the ?electrical specifications? on page 6. once selected, the compensation values in equation 41 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 41 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 22). keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 23, provides the necessary compensation. the first step, is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient per formance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a figure 22. compensation configuration for load-line regulated isl6313 circuit isl6313 comp c c r c r fb fb vsen c 2 (optional) 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v p-p lc ? ?? ? ? v in ---------------------------------------------------------- ? = c c v in 2 v p-p r fb f 0 ?? ? ? ----------------------------------------------------- - = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v p-p 2 ? () ? 2 f 0 2 lc ??? v in ----------------------------------------------------------------- - ? = c c v in 2 ? () 2 f 0 2 v p-p r fb lc ? ?? ? ? -------------------------------------------------------------------------------------- - = case 2: (eq. 41) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v p-p l ?? ? ? v in esr ? --------------------------------------------- - ? = c c v in esr c ?? 2 v p-p r fb f 0 l ?? ? ? ? ----------------------------------------------------------------- - = case 3: figure 23. compensation circuit without load-line regulation isl6313 comp c c r c r fb fb vsen c 2 c 1 r 1 isl6313
29 fn6448.2 september 2, 2008 good general rule is to choose f hf = 10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equation 41, r fb is selected arbitrarily. the remaining compensation components are then selected in equation 42. in equation 42, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in the electrical specifications on page 6. output filter design the output inductors and the output capacitor bank together to form a low-pass filter re sponsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount as shown in equation 43. the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively lo w capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as th e bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 10 and equation 2), a voltage develops across the bulk capacitor esr equal to i c(p-p) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance as shown in equation 44. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 45 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 46 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be se lected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. c c v in 2 f hf lc ? 1 ? ?? ? () ? 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = r c v p-p 2 ?? ?? ? 2 f 0 f hf lcr fb ?? ??? v in 2 f hf lc ? 1 ? ?? ? () ? ----------------------------------------------------------------------------------------- - = r 1 r fb cesr ? lc ? c esr ? ? ------------------------------------------- - ? = c 1 lc ? c esr ? ? r fb ------------------------------------------- - = c 2 v in 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = (eq. 42) vesl di dt ---- - ? esr i ? + (eq. 43) l esr v in nv ? out ? ?? ?? v out ? f s v in v p-p max () ?? ------------------------------------------------------------------- - ? (eq. 44) l 2ncv o ??? i () 2 --------------------------------- v max iesr ? () ? ? (eq. 45) isl6313
30 fn6448.2 september 2, 2008 switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in ?mosfets? on page 24, and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determined by the selection of the frequency-setting resistor, r s . figure 24 and equation 47 are provided to assist in selecting the correct value for r s . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a two-phase design, use figure 25 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l(p-p) ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. figure 26 provides the same input rms current information for single-phase designs. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. l 1.25 nc ?? i () 2 ---------------------------- - v max i esr ? () ? v in v o ? ?? ?? ?? (eq. 46) r s 10 10.61 1.035 f s () log ? () ? [] = (eq. 47) figure 24. r s vs switching frequency 10 100 500 50 100 1k 2k switching frequency (khz) r s (k ) figure 25. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 26. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in /v o ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6313
31 fn6448.2 september 2, 2008 layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a isl6313 controller. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed first, which include the mosfets, input and output capacitors, and the inductors. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidist ant placement of the controller to the power trains it contro ls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and simila r drive capability of all sets of mosfets. when placing the mosfets try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input bulk capacitors should be placed close to the drain of the upper fe ts and the source of the lower fets. locate the output inductors and output capacitors between the mosfets and the load. the high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next or on the capacitor solder pad. the critical small components include the bypass capacitors for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense components. locate the vcc/pvcc bypass capacitors as close to the isl6313 as possible. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. figure 27 shows the connections of the critical components for the converter. note that capacitors c xx(in) and c xx(out) could each represent numerous physical capacitors. dedicate one solid layer, usually the one u nderneath the com ponent side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to output inductors short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to reduce their overall impedance and inductance. they s hould be sized to carry at least one ampere of current (0.02? to 0.05?). going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibilit y of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. current sense component placement and trace routing one of the most critical aspec ts of the isl6313 regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sense components must be placed as close to their respective isen+ and isen- pins on the isl6313 as possible. the sense traces that connect the r-c sense components to each side of the output induc tors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or pla nes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performanc e in high current, high switching frequency applicatio ns, connecting the thermal gnd pad of the isl6313 to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part. isl6313
32 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6448.2 september 2, 2008 via connection to ground plane island on power plane layer island on circuit plane layer key figure 27. printed circuit board power planes and islands heavy trace on circuit plane layer c boot1 r 1 c 1 c 3 r ofs r fb c bin1 (c hfout ) c bout (cf1) (cf2) r t c ref locate close to ic locate near load; (minimize connection locate near switching transistors; (minimize connection path) (minimize connection path) vid4 vid5 pgood vid3 vid2 vid1 vcc isl6313 vid0 fs ofs ref load vrsel en gnd vid6 vid7 ss +5v isen2- isen2+ isen1- isen1+ +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc r ss c boot2 c bin2 c 1 r 1 c 1 r 1 path) iout r iout apa comp fb dvc vsen rgnd +5v vcc rset c 2 r 2 r dvc c dvc r apa r set isl6313
33 fn6448.2 september 2, 2008 isl6313 package outline drawing l36.6x6 36 lead thin quad flat no-lead plastic package rev 5, 08/08 bottom view side view typical recommended land pattern top view dimensioning and tolerancing conform to amsey14.5m-1994. dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. tiebar shown (if present) is a non-functional feature. unless otherwise specified, tolerance : decimal 0.05 4. 5. 6. 3. 2. dimensions are in millimeters. 1. located within the zone indicated. the pin #1 indentifier may be either a mold or mark feature. c detail "x" 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 6.00 a b 6.00 (4x) 0.15 6 pin 1 index area 28 pin #1 index area 36 32x 0.50 4.15 +0.10/-0.15 9 1 27 19 18 36x 0.55 0.10 10 6 4x 4.00 max 0.80 see detail "x" 0.08 0.10 c c c ( 5.65 ) ( 4.15) (36x 0.75) (36x .25) ( 32x 0.50) ( 5.65 ) ( 4x 4.00) exp. dap. ( 4.15) exp. dap. 0.10 36x 0.25 +0.05/-.07 a m c b 4

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